Efficient Fault Detection Architecture Design of Latch-based Low Power DSP/MCU Processor

被引：5

作者：

Yu, Hai ^{[1
]}

Nicolaidis, Michael ^{[1
]}

Anghel, Lorena ^{[1
]}

Zergainoh, Nacer-Eddine ^{[1
]}

机构：

[1] UJF, INPG, CNRS, TIMA Lab, Grenoble, France

来源：

2011 16TH IEEE EUROPEAN TEST SYMPOSIUM (ETS) | 2011年

关键词：

soft error; GRAAL; fault detection; DSP; SETs;

D O I：

10.1109/ETS.2011.20

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Soft errors have been emerged as an important reliability concern of modern ICs. In this work we have implemented an efficient error detection scheme in a low power DSP/MCU processor. Our scheme achieves high error detection efficiency at low hardware cost by means of an original combination of double-sampling and latch based-design into the so-called GRAAL architecture. The implementation of our design in 65nm and 45nm process nodes has confirmed the advantages of the GRAAL architecture: low area and power penalties and negligible performance degradation. Its high error detection efficiency was demonstrated by performing extensive simulations of single-event transients (SETs).

引用

页码：93 / 98

页数：6

共 18 条

[1]

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[2]

Bastos R.P., 2006, IOLTS 06

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