Programmable 28nm Coprocessor for HEVC/H.265 In-Loop Filters

被引：0

作者：

Hautala, Ilkka ^{[1
]}

Boutellier, Jani ^{[1
]}

Silven, Olli ^{[1
]}

机构：

[1] Univ Oulu, Dept Comp Sci & Engn, Oulu, Finland

来源：

2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2016年

关键词：

HEVC; in-loop filtering; Multicore; TTA; VLSI;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

High Efficiency Video Coding (HEVC) in-loop filtering includes the deblocking filter (DF) and the sample adaptive offset filter which consume about 20% of the total HEVC decoding time. In this paper a very energy efficient programmable multicore coprocessor for HEVC in-loop filtering is proposed. The coprosessor is placed and routed using leading edge 28nm technology to show that it can be clocked at 1.2 GHz while power consumption is only 207mW including memories. The design is able to filter 101 1080p intra frames per second. The cores can be reprogrammed using a high level language which enables use the high performance coprocessor also for other signal processing algorithms. The proposed coprocessor offers a new alternative between fixed accelerators and general purpose processors for mobile devices in terms of energy efficiency and programmability.

引用

页码：1570 / 1573

页数：4

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