Fast Implementation for the Singular Value and Eigenvalue Decomposition Based on FPGA

A fast and efficient hardware implementation for computing the Singular value decomposition (SVD) and Eigenvalue decomposition (EVD) is presented. Considering that the SVD and EVD are complex and expensive operations, to achieve high performance with low computing complexity, our approach takes full advantage of the combination of parallel and sequential computation, which can increase efficiently the hardware utilization. Besides, regarding to EVD, we propose a hardware solution of a simplified Coordinate rotation digital computer (CORDIC)-like algorithm which can obtain higher speed. The performance analysis and comparison results show that the proposed methods can be realized on Filed programmable gate arrays (FPGAs) with less computation time by using systolic array. It will be shown that the proposed implementation could be an efficient alternative for real-time applications.