A Modular-Logarithmic Coprocessor Concept

被引：4

作者：

Osinin, Ilya ^{[1
]}

机构：

[1] All Russian Res Inst Expt Phys, FSUE Russian Fed Nucl Ctr, Sarov, Russia

来源：

2017 INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING & SIMULATION (HPCS) | 2017年

基金：

俄罗斯科学基金会;

关键词：

coprocessor; residue number system (RNS); logarithmic number system (LNS); reconfigurable architecture; highly reliable computing;

D O I：

10.1109/HPCS.2017.93

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The paper presents a conceptual design of an IP module of mathematical coprocessor. It consists of a set of processing cores of the same kind which perform single-cycle scalar, or vector operations with real numbers. The processed data is represented in the modular logarithmic format that provides two levels of translating the original numbers, namely: the modular level instead of the conventional positional system and the logarithmic level instead of the floating point format. Owing to this feature a coprocessor has a higher performance, a higher accuracy and a higher level of reliability, as compared to the known analogs. A prototype coprocessor is an FPGA-based IP module. Companies developing general-purpose processors are the target market for this design.

引用

页码：588 / 594

页数：7