FPGA Implementation of True Random Number Generator Architecture Using All Digital Phase-Locked Loop

This study is a unique approach for the design and implementation of True Random Number Generator (TRNG) using ADPLL, on Field-Programmable Gate Array (FPGA) board Artrix-7 (XC7A35T-CPG236-1) and the simulation was done on Vivado v.2015.2 design suite. TRNG is solely based on the different seeds of entropy like Jitter, and metastability was produced from Ring Oscillator, Flip Flop (FF) and other primitives. In this paper, we have realized and implemented two architectures based on the use of ADPLL. TRNG with single ADPLL is represented as Novel design-1 (ND-1) and TRNG with two ADPLL as Novel design-2 (ND-2) cascading with other primitive like ring Oscillator combined with FF. Different from other approaches, this proposed TRNG architecture has higher speed, consumes less power in spite of employing 2 Look-Up-Tables (LUTs) and 1 slice block without compromising the overall throughput producing at 680.7 Mbps for ND-1 (Single ADPLL) and 676 Mbps for ND-2 (Two ADPLL). Comparing with other existing designs in the Field of TRNG and found out to have higher throughput and less power consumption, less complexity by employing a reduced FPGA hardware resource. Digital storage oscilloscope (DSO) is used to capture output waveform and FFT waveform for both ND-1 (single ADPLL) and ND-2 (two ADPLL). The randomness of the generated bitstream output of the design architecture is validated by passing the NIST SP 800-22 test which evidences that the proposed ADPLL-based TRNG can be better suited for different industrial applications such as security Network system, cybersecurity, Banking security, IIOT, IOT.