Implementation of a self-timed segmented bus

被引：0
作者：
Lombardi, F [1 ]
机构：
[1] Northeastern Univ, Boston, MA 02115 USA
来源：
IEEE DESIGN & TEST OF COMPUTERS | 2003年 / 20卷 / 06期
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中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
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页码：44 / 44
页数：1
相关论文
共 11 条
[1]  
*ARM LTD, 1999, AMBA SPEC REV 2 0
[2]   Asynchronous macrocell interconnect using MARBLE [J].
Bainbridge, WJ ;
Furber, SB .
ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS - FOURTH INTERNATIONAL SYMPOSIUM, 1998, :122-132
[3]  
CHAPIRO DM, 1984, THESIS STANFORD U
[4]   Segmented bus design for low-power systems [J].
Chen, JY ;
Jone, WB ;
Wang, JS ;
Lu, HI ;
Chen, TF .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1999, 7 (01) :25-29
[5]  
DALLY WJ, 1998, DIGITAL SYSTEMS
[6]   ASYNCHRONOUS DESIGN METHODOLOGIES - AN OVERVIEW [J].
HAUCK, S .
PROCEEDINGS OF THE IEEE, 1995, 83 (01) :69-93
[7]  
KATSINIS C, 1997, P INT C PAR DISTR CO
[8]  
KOTSIS G, 1993, PARS MITTEILUNGEN, V11, P1
[9]   AN APPROXIMATION ALGORITHM FOR SCHEDULING TASKS ON VARYING PARTITION SIZES IN PARTITIONABLE MULTIPROCESSOR SYSTEMS [J].
KRISHNAMURTI, R ;
MA, E .
IEEE TRANSACTIONS ON COMPUTERS, 1992, 41 (12) :1572-1579
[10]  
LEE S, 1999, P AS PAC C CHIP DES, P144
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