Methodology of Generating Timing-Slack-Based Cell-Aware Tests

被引:3
作者
Nien, Yu-Teng [1 ]
Wu, Kai-Chiang [2 ]
Lee, Dong-Zhen [3 ]
Chen, Ying-Yen [3 ]
Chen, Po-Lin [3 ]
Chern, Mason [3 ]
Lee, Jih-Nung [3 ]
Kao, Shu-Yi [3 ]
Chao, Mango Chia-Tso [1 ]
机构
[1] Natl Yang Ming Chiao Tung Univ, Dept Elect Engn & Inst Elect, Hsinchu 30010, Taiwan
[2] Natl Yang Ming Chiao Tung Univ, Dept Comp Sci, Hsinchu 30010, Taiwan
[3] Realtek Semicond Corp, CTC DFT, Hsinchu 300, Taiwan
关键词
Circuit faults; Delays; Integrated circuit modeling; Voltage measurement; Transistors; Standards; Analytical models; Automatic test pattern generation (ATPG); cell-aware (CA) test; defect-based test; delay testing;
D O I
10.1109/TCAD.2021.3135785
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In order to reduce defect parts per million, cell-aware (CA) methodology was proposed to cover various types of intracell defects. In this article, we present a novel methodology for generating 2-time-frame (2tf) CA tests based on timing slack analysis. The proposed 2tf CA fault model, aware of timing slack and named TS, defines a fault: 1) on a cell instance basis and 2) based on per-instance timing criticality (according to timing slack). By comparing the derived extra delay against the timing slack of the cell instance, a delay fault can be defined, and according to its severity, the fault can be further classified into small-delay fault or gross-delay fault. In contrast to prior 2tf CA methodology that is on a cell (rather than cell instance) basis and unaware of timing criticality/slack, our methodology can identify "more realistic" faults which really need to be considered, and potentially the cost/effort for testing those 2tf CA faults can be reduced. We also propose a test quality metric, timing slack defect coverage (TSDC), to measure the effectiveness of automatic test pattern generation (ATPG) tests in terms of the ability to detect small-delay TS defects along long paths. Experimental results on a set of 22-nm industrial designs demonstrate that, due to more realistic fault identification, the number of identified small-delay faults can be reduced by 56.8%. With the slack-based ATPG for testing small-delay faults along long paths, TS can reduce the number of test patterns by 33.1% while achieving 0.49% higher TSDC, compared with the results of prior 2tf CA methodology.
引用
收藏
页码:5057 / 5070
页数:14
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