An Efficient Design of a Parallel Prefix Adder based on QCA Technology

This paper presents an optimized Parallel Prefix Adders (PPA) based on Quantum dot Cellular Automata (QCA) technology. PPA presents the most used block in Arithmetic Logic Units (ALU) which presents a fundamental part in several digital integrated circuits. The classical implementation method of PPA based on traditional Complementary Metal Oxide Semiconductor (CMOS) Technology presents several problems in terms of frequency, power consumption, surface and others. The QCA technology offers several features such as ultralow power consumption, small size, and can operate up to 1 THz. In this work, a 4-bit Parallel Prefix Adder with a new prefix low area and high speed is proposed. The proposed design is based on a half-adder circuit and other logic gates. These designs were tested and simulated using the freely known QCA Designer Tool version 2.0.3. and QCA pro. The proposed Half-adder presents a reduction of 23% 46% and 36% in terms of cell count, latency and power consumption, respectively compared to existing designs. The proposed PPA design shows almost an optimization of 5% in area and 58% in latency compared to the RCA design. The proposed circuit present an optimization of 20% in term of energy consumption compared to the existing PPA 4-bit Brent Kung Adder design.