A foreground digital calibration algorithm for time-interleaved ADCs with low computational complexity

In front of the offset, gain, timing, and bandwidth mismatch errors, time-interleaved analog-to-digital convert-ers (TIADCs) are usually calibrated to achieve satisfying performance. In this paper, we propose a new digital calibration approach for TIADCs, including the direction-distance search algorithm and multiplier-free gradient descent method. Compared to state-of-the-art multiplication-less techniques, this approach significantly reduces time complexity by minimizing search space dimension, subtracting the number of searches, and varying iteration step size. Notably, no multiplier is needed in the mismatch estimation, resulting in a much lower computational complexity than in previous work. For a 12-bit 4-channel TIADC, simulation results show that the signal-to-noise-and-distortion ratio is improved from 25 dB to 65 dB within the duration of 1600 samples. The proposed calibration circuit is synthesized targeting standard 28-nm technology, occupying the area of 0.014 mm2 and dissipating the power of 19 mW at 2.8 GHz clock frequency.