A 7-19 GHz CMOS Low Power LNA Using Body Bias and Current-Reuse Technique

A low power wideband low noise amplifier (LNA) using body bias and current-reuse technique is presented in this paper. Through biasing the body voltage at a higher level than the source voltage, the threshold voltage of the transistor can be significantly lowered, and then the drain of the transistor can be biased at a lower level, thus reducing DC power dissipation. In addition, current-reuse technique is also used to further reduce DC power consumption. Transformer-based input match network which can introduce three poles is used to extend the bandwidth of the low noise amplifier. A prototype with 3dB bandwidth from 6.8 to 19.2 GHz is designed, fabricated, and measured using a 55nm CMOS process. The measured noise figure (NF) ranges from 3.0 to 4.7 dB over the gain bandwidth, while the measured input 1dB gain compression point (IP-1dB) ranges from -17.1 to -13.7 dBm, and the DC dissipation current is only 5.9 mA from 1V supply.