A Scalable Enhancement-Mode Junctionless SiC FET with Embedded P+ Pockets in the Oxide Layer for High-Temperature Applications

Junctionless FETs exhibit better high-temperature performance than their traditional inversion-mode (IM) counterparts due to reduced scattering in the substrate-oxide interfaces. In this work, a double-gate junctionless SiC FET with an embedded P+ pocket in the oxide layer (P+-SiCJLT) is studied for DC and AC performance for high-temperature and high-voltage applications using calibrated TCAD simulations. The advantages of P+-SiCJLT are manifold: (a) it offers efficient volume depletion and therefore can be scaled to lower channel lengths, (b) it improves the ON-state to OFF-state current ratio, (c) it improves the intrinsic gain, and (d) it promotes enhancement-mode operation in traditional depletion-mode FETs. These advantages become apparent when the P+-SiCJLT is compared with a device of similar dimensions without the P+ layer (SiCJLT). Moreover, P+-SiCJLT offers better electrostatics and ION/IOFF\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$${{I}}_{{ON}}/{{I}}_{{OFF}}$$\end{document} ratio than a SiCJLT with P+ pockets near the source/drain regions (SDPocket-SiCJLT).