Cell-Based Aging Sensor Using Built-In Speed Grading

被引:1
作者
Lin, Ont-Derh [1 ]
Huang, Shi-Yu [1 ]
机构
[1] Natl Tsing Hua Univ, Elect Engn Dept, Hsinchu, Taiwan
来源
2023 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE, NORCAS | 2023年
关键词
Aging Sensor; Built-In Speed Grading; BIST; Cell-Based PLL; Infant-Mortality; FREQUENCY;
D O I
10.1109/NorCAS58970.2023.10305452
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Built-In Speed Grading (BISG) is a technique that measures the maximum operating speed (Fmax) of a circuit under test in silicon. Traditionally, it has been used in supporting performance debugging as well as Dynamic Voltage and Frequency Scaling. Recently, it has also been used to accelerate the detection of infant-mortality-prone devices and lifetime prediction during the stress test process. In this paper, we demonstrate that it can be used as an effective aging sensor. Compared to previous work, our BISG design presented in this paper enjoys an area reduction of 43.4%. It supports a wide clock frequency range of [40MHz, 1.25GHz] using only a 90nm CMOS process while achieving a fine-tuning resolution of 1%. Furthermore, it is made of standard cells and thereby rendering easy process migration. These above features combined make it not only a cost-effective but also a trustworthy on-chip aging sensor.
引用
收藏
页数:6
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