共 43 条
[31]
Meswani MR, 2015, INT S HIGH PERF COMP, P126, DOI 10.1109/HPCA.2015.7056027
[32]
A Software-managed Approach to Die-stacked DRAM
[J].
2015 INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURE AND COMPILATION (PACT),
2015,
:188-200
[33]
MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories
[J].
2017 23RD IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA),
2017,
:433-444
[34]
Fundamental Latency Trade-offs in Architecting DRAM Caches Outperforming Impractical SRAM-Tags with a Simple and Practical Design
[J].
2012 IEEE/ACM 45TH INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO-45),
2012,
:235-246
[35]
Qureshi MK, 2009, CONF PROC INT SYMP C, P24, DOI 10.1145/1555815.1555760
[36]
Qureshi MoinuddinK., 2011, SYNTHESIS LECT COMPU, V6, P1
[37]
Ramos Luiz E., 2011, P INT C SUP ICS, P85
[38]
SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization
[J].
2017 23RD IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA),
2017,
:349-360
[39]
Transparent Hardware Management of Stacked DRAM as Part of Memory
[J].
2014 47TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO),
2014,
:13-24
[40]
Smullen CW IV, 2011, INT S HIGH PERF COMP, P50, DOI 10.1109/HPCA.2011.5749716