Energy Efficient Compressor Cell for Low Power Computing

被引:0
作者
Upadhyay, Rahul Mani [1 ]
Chauhan, R. K. [1 ]
Kumar, Manish [1 ]
机构
[1] Madan Mohan Malaviya Univ Technol, Gorakhpur, Uttar Pradesh, India
来源
ADCAIJ-ADVANCES IN DISTRIBUTED COMPUTING AND ARTIFICIAL INTELLIGENCE JOURNAL | 2023年 / 12卷 / 01期
关键词
full adder; delay; power dissipation; power-delay product; XOR-XNOR gates; APPROXIMATE; 4-2; COMPRESSORS; DESIGN; MULTIPLIERS;
D O I
10.14201/adcaij.30381
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
As the use of multimedia devices is rising, power management is becoming a major challenge. Various types of compressors have been designed in this study. Compressor circuits are designed using several circuits of XOR-XNOR gates and multiplexers. XOR-XNOR gate combinations and multiplexer circuits have been used to construct the suggested compressor design. The performance of the proposed compressor circuits using these low-power XOR-XNOR gates and multiplexer blocks has been found to be economical in terms of space and power. This study proposes low-power and high-speed 3-2, 4-2, and 5-2 compressors for digital signal processing applications. A new compressor has also been proposed that is faster and uses less energy than the traditional compressor. The full adder circuit, constructed using various combinations of XOR-XNOR gates, has been used to develop the proposed compressor. The proposed 3-2 compressor shows average power dissipation 571.7 nW and average delay 2.41 nS, 4-2 compressor shows average power dissipation 1235 nW and average delay 2.7 nS while 5-2 compressor shows average power dissipation 2973.50 nW and average delay 3.75 nS.
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页数:15
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