A Fast-Transient mitigation technique for a dual-loop, linear search, self-timed, Asynchronous Digital LDO

In this paper is presented a fast-transient mitigation technique which applies to a self-timed, dual-loop Asynchronous Digital LDO. The number of conducting transistors is controlled by an Asynchronous Finite State Machine (AFSM) employing a linear-search algorithm that is able to operate without a clock oscillator. It relies on a simple Request-Acknowledge (REQ-ACK) protocol to manage the power stage. The proposed mitigation technique has two components. One relies on using a secondary loop that has bigger transistors. The LDO reaches steady state faster than the main loop due to the higher adjustment steps. The other component controls the operating frequency by altering the REQ-ACK protocol in order to sample and update the output faster. The circuit was simulated and fabricated using Infineon's proprietary 130nm BCD technology and was assembled in SSOP-14 plastic package. Also, the proposed circuit was measured and the results show more than 50 percent improvement and a settle time reduction with a factor of 4 on sudden load changes while a light increase in output voltage ripple for steady-state operation must be considered.