共 43 条
[1]
Alle M, 2013, DES AUT CON
[2]
AMD Xilinx, 2023, Vitis High-Level Synthesis User Guide (UG1399)
[3]
Bhowmik A., 2002, P 14 ACM S PARALLEL, P99
[4]
A Practical Automatic Polyhedral Parallelizer and Locality Optimizer
[J].
PLDI'08: PROCEEDINGS OF THE 2008 SIGPLAN CONFERENCE ON PROGRAMMING LANGUAGE DESIGN & IMPLEMENTATION,
2008,
:101-+
[5]
Canis A, 2011, FPGA 11: PROCEEDINGS OF THE 2011 ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD PROGRAMMABLE GATE ARRAYS, P33
[7]
Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis
[J].
FPGA'17: PROCEEDINGS OF THE 2017 ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE GATE ARRAYS,
2017,
:189-194
[9]
Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits
[J].
PROCEEDINGS OF THE 2023 ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD PROGRAMMABLE GATE ARRAYS, FPGA 2023,
2023,
:39-45
[10]
Elliott J.P., 1999, Understanding Behavioral Synthesis: A Practical Guide to High-Level Design