A 0.9-V 50-MS/s 67.3-dB-SNDR SAR-ISDM ADC With an Oscillator-Based Integrator

被引：2

作者：

Chan, Yen-Chun ^{[1
]}

Chang, Che-Wei ^{[1
]}

Lee, Tai-Cheng ^{[2
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan

[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2023年 / 70卷 / 09期

关键词：

SAR ADC; incremental sigma-delta modulator; ring oscillator; CMOS;

D O I：

10.1109/TCSII.2023.3262998

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A two-step analog-to-digital converter (ADC), using a successive approximation register (SAR) ADC and a timedomain incremental Sigma Delta modulator (ISDM) for the coarse and fine conversion, is proposed for power-efficient data conversion. A high-gain gated-delay oscillator (GDO) with a time-domain integration technique is employed to achieve the first-order noise shaping in the fine ISDM conversion. The proposed ADC fabricated in a 40-nm CMOS technology achieves a peak SNDR of 67.3 dB, the Schreier figure of merit (FoMS) of 169.27 dB, and the Walden figure of merit (FoMW) of 16.76 fJ/conversion-step.

引用

页码：3263 / 3267

页数：5

共 13 条

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