Design of Dual-Delay-Path Low-Power VCRO with I-MOS Varactor Tuning

This paper presents a novel low-power four-stage voltage controlled ring oscillator (VCRO) designed in the TSMC 180 nm CMOS technology. Each stage in the proposed VCRO consists of a differential delay cell. Output frequency tuning is controlled by the I-MOS varactor connected at the output of each delay stage. Different performance parameters, including tuning range, power consumption, phase noise and figure of merit, have been obtained in the TSMC 180 nm CMOS technology. Results show that the output oscillation frequency of VCRO is tunable from 0.545 to 1.195 GHz by varying the drain/source voltage (V-ids) from 0.6 to 1.8 V with a supply voltage (V-dd) of 1.8 V. Furthermore, it provides a wide tuning range from 0.152 to 1.903 GHz with the variation in V-dd from 1 to 3 V with different I-MOS widths of 0.5, 1, 2 and 4 mu m. Furthermore, effects of change in V-ids from 0.8 to 1.8 V with V-dd variations from 1 to 3 V have been evaluated with I-MOS varactor width (W) of 2 mu m. Frequency range from 0.170 to 1.451 GHz has been achieved for this tuning method. The proposed VCRO exhibits the phase noise of -100.45 dBc/Hz @1 MHz and -96.01 dBc/Hz @0.6 MHz from the centre frequency with power consumption 0.003 to 3.165 mW with a change in V-dd from 1.8 to 3.0 V. The figure of merit (FoM) of the proposed VCRO is 161.77dBc/Hz.