共 42 条
Online Digital Implementation of Wide Voltage Range RMS-Current-Optimized Control With Voltage Balancing Capability for DAB Converter
被引:10
作者:
Yang, Jiangpeng
[1
]
Shu, Zeliang
[2
]
Wang, Tianxiang
[1
]
Xiang, Shibiao
[1
]
Nie, Jianglin
[1
]
Wang, Shun
[1
]
Lei, Yuan
[1
]
Ma, Lan
[1
]
机构:
[1] Southwest Jiaotong Univ, Sch Elect Engn, Chengdu 611756, Peoples R China
[2] Southwest Jiaotong Univ, Key Lab Magnet Suspens Technol & Maglev Vehicle, Minist Educ, Chengdu 611756, Peoples R China
基金:
中国国家自然科学基金;
国家重点研发计划;
关键词:
Inductors;
Zero voltage switching;
Modulation;
Bridge circuits;
Switches;
Voltage control;
Optimization;
Dual active bridge (DAB);
online implementation scheme;
optimized triple-phase-shift (OTPS) scheme;
variable parameter control (VPC);
voltage balancing capability;
DC-DC CONVERTER;
ACTIVE-BRIDGE CONVERTER;
SOFT-SWITCHING RANGE;
PHASE-SHIFT CONTROL;
MODULATION SCHEME;
REACTIVE POWER;
STRATEGY;
EXTEND;
ZVS;
DESIGN;
D O I:
10.1109/TPEL.2022.3227177
中图分类号:
TM [电工技术];
TN [电子技术、通信技术];
学科分类号:
0808 ;
0809 ;
摘要:
The dual active bridge (DAB) converter is widely used in renewable energy power generation systems with wide input voltage characteristics. An inappropriate duty cycle will lead to a larger inductor root-mean-square (RMS) current and low efficiency. In this article, an efficiency-oriented optimized triple-phase-shift (OTPS) scheme is proposed for the DAB converter that can reduce the inductor rms current for a wide input voltage and realize zero-voltage switching (ZVS). The ZVS condition contains the direction and amplitude of the inductor current to make the ZVS area more accurate. In addition, the OTPS scheme also has the capability of voltage balancing without additional voltage equalizers under unbalanced load. The influence of deadtime on voltage balance is analyzed and a voltage balancing scheme with compensation of the duty cycle is proposed. To reduce resource occupation and operation time, an online implementation scheme of variable parameter control based on field-programable gate array (FPGA) is proposed. Without a look-up table, the sum of the operation time of the control module and modulation module is only 0.66 $\mu$s, and the required memory bits are only 459 k. Both operation time and memory bits are reduced by more than 90% compared to the existing literature. Finally, the whole proposed process is verified by the experimental results.
引用
收藏
页码:4360 / 4377
页数:18
相关论文