Design of Fail-Safe Window Comparator Circuits Using Unconditional Deterministic Optimization

The window comparator circuit operates by comparing the input signal's level with a predetermined range of levels. If the signal falls within this specified range, the output will be set to a "High" logic signal; otherwise, it will be set to a "Low" logic signal. Fail-safe window comparator circuits find application in fault detection systems, particularly in scenarios that require high -precision and stable analog circuits. They are designed to be intrinsically safe, ensuring that in the event of any circuit failure, the output signal will consistently remain in a logical "Low" state. The design concept relies on an AND logic circuit that operates through transistor oscillation. This oscillation is determined by the specific values of resistances and input voltages. This paper introduces a methodology for designing fail-safe window comparator circuits across multiple voltage ranges. The approach involves optimizing the circuit's resistance values to accurately establish the boundaries of the upper and lower windows. This is achieved through the application of an optimization method that employs unconditional deterministic optimization techniques, specifically the maximum and minimum methods. The optimization conditions were assessed using the Scilab program, while circuit testing was conducted using the LTspice program.