Gate Bias Effects on Hydrogen-Terminated Polycrystalline Diamond FETs

In this article, gate bias (V-GS,V-stress) effects on the hydrogen (H)-terminated polycrystalline diamond field effect transistors (FETs) are investigated. A 7- to 8-nmAlOxinterface layer is found between the Al metal and polycrystalline diamond by electrical and microstructure characterization. The threshold voltage (VTH) and ON-resistance (Ron) exhibit different changing trends under varying V-GS,V-stress. Specifically, a bidirectional shift of VTH is observed during gate bias stress. To explain the distinct behavior of V-TH shift and R-ON change occurring under gate bias, holes trapping by defects, H-motion, and sur-face leakage electron trapping models are proposed. Under negative gate bias, holes in 2-D hole gas channel are captured by the interface states and/or defects in the AlOx layer, resulting in a negative shift of V-TH. Simultaneously, H-motion in the AlOx layer under gate bias leads to the generation of negative charges. Additionally, electrons in the surface leakage path are trapped by defects on the diamond surface in the access region, leading to decreased access region resistance. For a harsh gate bias, a high density of new defects is generated, and a defect density changes from 4.9 x 10(21)ev(-1)cm(-3)for the fresh device to 5.1 x 10(23)ev(-1)cm(-3)for the device after gate bias(V-GS,V-stress= -4 V) which is characterized by using the low-frequency noise measurements. These findings high-light the importance of surface passivation and high-quality gate dielectric in suppressing charging effects and new defect generation in H-terminated polycrystalline diamond FETs, ultimately contributing to device stability.