Design of Radiation Hardened 12T SRAM with Enhanced Reliability and Read/Write Latency for Space Application

被引:3
作者
Ansari, Mohd Sakib S. [1 ]
Kavitha, S. [1 ]
Reniwal, B. S. [2 ]
Vishvakarma, S. K. [3 ]
机构
[1] Indian Inst Informat Technol Design & Mfg IIITDM, Kancheepuram, India
[2] Indian Inst Technol, Jodhpur, Rajasthan, India
[3] Indian Inst Technol, Indore, India
来源
2023 36TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2023 22ND INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, VLSID | 2023年
关键词
Soft Errors; Single Event Upset (SEU); Static Noise Margin (SNM); Read Delay; Write Delay; Critical Charge; SRAM; CELL;
D O I
10.1109/VLSID57277.2023.00034
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Soft Errors becoming more predominant due to the constant scaling down of the transistors which lead to a decrease in the critical charge (Qc) and noise margin of the memory cell. In this paper, radiation-hardened (RH) 12T Memory cell is proposed which is resilient to soft errors as well as improves the critical read and write access time. This memory cell exhibits better results in terms of critical charge Qc with improved write static noise margin (WSNM). The extensive Monte Carlo simulations in Industry Hardware Calibrated 65nm standard CMOS process demonstrates that the proposed cell achieves improved performance with respect to 0.70x read access time, 0.69x write access time, 4.57x WSNM, 1.07x Q(c) as compared to NQ-10T at a supply voltage of 1V. Qc of the proposed RH-12T outperforms 6T SRAM & Q-10T by 1.91x and 1.62x respectively. In terms of area comparison, the silicon area is 1x for both NQ-10T and the proposed 12T.
引用
收藏
页码:104 / 108
页数:5
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