Yield Optimization for Analog Circuits over Multiple Corners via Bayesian Neural Networks: Enhancing Circuit Reliability under Environmental Variation

被引:0
作者
Guo, Nanlin [1 ]
Peng, Fulin [1 ]
Shi, Jiahe [1 ]
Yang, Fan [1 ]
Tao, Jun [1 ]
Zeng, Xuan [1 ]
机构
[1] Fudan Univ, Sch Microelect, State Key Lab Integrated Chips & Syst, Shanghai 200433, Peoples R China
基金
国家重点研发计划; 中国国家自然科学基金;
关键词
Bayesian neural network; Bayesian optimization; yield optimization; analog circuits; PVT corners; hardware reliability; EFFICIENT;
D O I
10.1145/3626321
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The reliability of circuits is significantly affected by process variations in manufacturing and environmental variation during operation. Current yield optimization algorithms take process variations into consideration to improve circuit reliability. However, the influence of environmental variations (e.g., voltage and temperature variations) is often ignored in current methods because of the high computational cost. In this article, a novel and efficient approach named BNN-BYO is proposed to optimize the yield of analog circuits in multiple environmental corners. First, we use a Bayesian Neural Network (BNN) to simultaneously model the yields and performances of interest in multiple corners efficiently. Next, the multi-corner yield optimization can be performed by embedding BNN into a Bayesian optimization framework. Since the correlation among yields and performances of interest in different corners is implicitly encoded in the BNN model, it provides great modeling capabilities for yields and their uncertainties to improve the efficiency of yield optimization. Our experimental results demonstrate that the proposed method can save up to 45.3% of simulation cost compared to other baseline methods to achieve the same target yield. In addition, for the same simulation cost, our proposed method can find better design points with 3.2% yield improvement.
引用
收藏
页数:17
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