Effect of Noncircular Channel on Distribution of Threshold Voltage in 3D NAND Flash Memory

被引:0
作者
Go, Donghyun [1 ]
Yoon, Gilsang [1 ]
Park, Jounghun [1 ]
Kim, Donghwi [1 ]
Kim, Jiwon [1 ]
Kim, Jungsik [2 ]
Lee, Jeong-Soo [1 ]
机构
[1] Pohang Univ Sci & Technol, Dept Elect Engn, Pohang 37673, South Korea
[2] Gyeongsang Natl Univ, Dept Elect Engn, Jinju 52828, South Korea
基金
新加坡国家研究基金会;
关键词
3D NAND flash memory; noncircular cell; spike; TCAD simulation; threshold voltage distribution; trapped charge;
D O I
10.3390/mi14112007
中图分类号
O65 [分析化学];
学科分类号
070302 ; 081704 ;
摘要
The instability in threshold voltage (VTH) and charge distributions in noncircular cells of three-dimensional (3D) NAND flash memory are investigated. Using TCAD simulation, we aim to identify the main factors influencing the VTH of noncircular cells. The key focus is on the nonuniform trapped electron density in the charge trapping layer (CTL) caused by the change in electric field between the circular region and the spike region. There are less-trapped electron (LT) regions within the CTL of programmed noncircular cells, which significantly enhances current flow. Remarkably, more than 50% of the total current flows through these LT regions when the spike size reaches 15 nm. We also performed a comprehensive analysis of the relationship between charge distribution and VTH in two-spike cells with different heights (HSpike) and angles between spikes (theta). The results of this study demonstrate the potential to improve the reliability of next-generation 3D NAND flash memory.
引用
收藏
页数:11
相关论文
共 28 条
  • [1] 7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing
    Barraud, S.
    Previtali, B.
    Vizioz, C.
    Hartmann, J. M.
    Sturm, J.
    Lassarre, J.
    Perrot, C.
    Rodriguez, Ph
    Loup, V
    Magalhaes-Lucas, A.
    Kies, R.
    Romano, G.
    Casse, M.
    Bernier, N.
    Jannaud, A.
    Grenier, A.
    Andrieu, F.
    [J]. 2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, 2020,
  • [2] Mitigating the Impact of Channel Tapering in Vertical Channel 3-D NAND
    Bhatt, Upendra Mohan
    Manhas, Sanjeev Kumar
    Kumar, Arvind
    Pakala, Mahendra
    Yieh, Ellie
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (03) : 929 - 936
  • [3] Memory Technology 2021: Trends & Challenges
    Choe, Jeongdong
    [J]. 2021 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2021), 2021, : 111 - 115
  • [4] Study of Plasma Arcing Mechanism in High Aspect Ratio Slit Trench Etching
    Chung, Yao-An
    Lung, Cheng-Yi
    Chiu, Yuan-Chieh
    Lee, Hong-Ji
    Lian, Nan-Tzu
    Yang, Tahone
    Chen, Kuang-Chao
    Lu, Chih-Yuan
    [J]. 2019 30TH ANNUAL SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE (ASMC), 2019,
  • [5] Numerical Study of Non-Circular Pillar Effect in 3D-NAND Flash Memory Cells
    Fayrushin, Albert
    Liu, Haitao
    Mauri, Aurelio
    Carnevale, Gianpietro
    Cho, Hyejin
    Mao, Duo
    [J]. 2019 IEEE WORKSHOP ON MICROELECTRONICS AND ELECTRON DEVICES (WMED), 2019, : 1 - 4
  • [6] BER Evaluation System Considering Device Characteristics of TLC and QLC NAND Flash Memories in Hybrid SSDs with Real Storage Workloads
    Fukuchi, Mamoru
    Suzuki, Shun
    Maeda, Kyosuke
    Matsui, Chihiro
    Takeuchi, Ken
    [J]. 2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2021,
  • [7] 3-D NAND Technology Achievements and Future Scaling Perspectives
    Goda, Akira
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (04) : 1373 - 1381
  • [8] Goda A, 2012, 2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
  • [9] Influence of accumulated charges on deep trench etch process in 3D NAND memory
    Han, Chen
    Wu, Zhipeng
    Yang, Chuan
    Xie, Liuqun
    Xu, Bo
    Liu, Liheng
    Yin, Zi
    Jin, Lei
    Huo, Zongliang
    [J]. SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2020, 35 (04)
  • [10] 3D NAND Flash Status and Trends
    Heineck, Lars
    Liu, Jin
    [J]. 2022 14TH IEEE INTERNATIONAL MEMORY WORKSHOP (IMW 2022), 2022, : 1 - 4