Implementation of Deep Learning Models on an SoC-FPGA Device for Real-Time Music Genre Classification

被引:8
作者
Faizan, Muhammad [1 ]
Intzes, Ioannis [2 ]
Cretu, Ioana [1 ]
Meng, Hongying [1 ]
机构
[1] Brunel Univ London, Coll Engn Design & Phys Sci, London UB8 3PH, England
[2] Int Hellenic Univ, Dept Informat & Elect Engn, Thessaloniki 57001, Greece
关键词
SoC; FPGA; deep learning; classification; CNN; LSTM; DNN; Vitis; AI;
D O I
10.3390/technologies11040091
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Deep neutral networks (DNNs) are complex machine learning models designed for decision-making tasks with high accuracy. However, DNNs require high computational power and memory, which limits such models to fitting on edge devices, resulting in unnecessary processing delays and high energy consumption. Graphical processing units (GPUs) offer reliable hardware acceleration, but their bulky sizes prevent their utilization in portable equipment. System-on-chip field programmable gated arrays (SoC-FPGAs) provide considerable computational power with low energy consumption, making them ideal for edge computing applications, owing to their innovative, flexible, and small design. In this paper, we implement a deep-learning-based music genre classification system on a SoC-FPGA board, evaluate the model's performance, and provide a comparative analysis across different platforms. Specifically, we compare the performance of long short-term memory (LSTM), convolutional neural networks (CNNs), and a hybrid model (CNN-LSTM) on an Intel Core i7-8550U by Intel Cooperation. The models are fed an acoustic feature called the Mel-frequency cepstral coefficient (MFCC) for training and testing (inference). Then, by using the advanced Vitis AI tool, a deployable version of the model is generated. The experimental results show that the execution speed is increased by 80%, and the throughput rises four times when the CNN-based music genre classification system is implemented on SoC-FPGA.
引用
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页数:18
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