Room-Temperature Direct Cu Semi-Additive Plating (SAP) Bonding for Chip-on-Wafer 3D Heterogenous Integration With μLED

被引:5
作者
Susumago, Yuki [1 ]
Liu, Chang [1 ]
Hoshi, Tadaaki [1 ]
Shen, Jiayi [1 ]
Shinoda, Atsushi [2 ]
Kino, Hisashi [3 ]
Tanaka, Tetsu [3 ]
Fukushima, Takafumi [3 ,4 ]
机构
[1] Tohoku Univ, Dept Mech Syst Engn, Sendai, Miyagi 9808579, Japan
[2] Tohoku Univ, Sch Mech Engn, Sendai 9808579, Japan
[3] Tohoku Univ, Dept Biomed Engn, Sendai, Miyagi 9808579, Japan
[4] Tohoku Univ, Dept Mech Syst Engn, Sendai, Miyagi 9808579, Japan
关键词
Heterogeneous integration; 3D-IC; mu LED; flexible hybrid electronics (FHE); direct bonding; chiplets; FLEXIBLE HYBRID ELECTRONICS; HIGH-PERFORMANCE; TECHNOLOGY; FOWLP; 3-D;
D O I
10.1109/LED.2023.3237834
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This letter describes a direct Cu bonding technology to there-dimensionally integrate heterogeneous dielets based on a chip-on-wafer configuration. 100 -mu m cubed blue mu LEDs temporarily adhered on a photosensitive resin are interconnected by semi-additive plating (SAP) without thermal compression bonding. By using SAP bonding, a lot of dielets can be stacked on thin 3D-IC chiplets. The following three key technologies are applied to solve the yield issues of SAP bonding. After pick and-place assembly, additional coplanarity enhancement eliminates Cu bridges grown to a small gap between the mu LEDs and photosensitive resin. The mu LEDs arrays with sidewalls insulated by room-temperature ozone-ethylene radical (OER)-SiO2-CVD are successfully bonded on sapphire wafers and a thin 3D-IC with through-Si via (TSV). Further design optimization is required, but partial seed pre-etching works well to increase the yield. Fully integrated module implementation with the 3D-ICs will be the next stage, however, we discuss a superior prospect for yield enhancement toward nearly 100%.
引用
收藏
页码:500 / 503
页数:4
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