A Novel Active Pixel Sensor Architecture with In-Pixel Chopping and Switched Biasing to Reduce the Low-Frequency Noise

被引:1
作者
Jainwal, Kapil [1 ]
Sarkar, Mukul [2 ]
机构
[1] Indian Inst Technol Bhilai, Elect Engn & Comp Sci, Bhilai, India
[2] Indian Inst Technol Delhi, Elect Engn, New Delhi, India
来源
2023 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS | 2023年
关键词
1/f noise; switched biasing; random-telegraph; signal (RTS) noise; chopping; random noise; dynamic range; MOSFET 1/F NOISE; TRANSISTORS; AMPLIFIERS; CIRCUIT; FILTER;
D O I
10.1109/ISCAS46773.2023.10181424
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
In this work, a novel low-noise active pixel sensor (APS) is proposed which deploys in-pixel chopping and switched biasing to reduce the temporal noise. The source follower (SF) of an APS is the major contributor of the temporal noise. The proposed sensor is a modified conventional 3T pixel with an nwell/psub photodiode (PD) as photo-sensing element. To implement in-pixel chopping, two minimal sized additional nMOS switches are used per pixel. The switched biasing is implemented using two column-level (ps and ns) switches without affecting the pixel fill-factor (FF). The noise reduction techniques are validated through measured results obtained from a prototype sensor fabricated in 350 nm OPTO process from AMS. The sensor consists of a 2-D array of 128x128 pixels. The proposed pixel is designed with an area of 11 mu mx11 mu m achieving a FF of 35%. A total noise reduction (and enhancement in dynamic range (DR)) of around 16 dB is achieved from in-pixel chopping with 8 MHz chopping frequency (f(ch)) and switched biasing.
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页数:5
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