A 105-525MHz Integer-N Phase-Locked Loop in Indigenous SCL 180nm CMOS

被引：2

作者：

Nigam, Shivam ^{[1
]}

Murali, Mukund ^{[2
]}

Gupta, Hari Shanker ^{[3
]}

Saxena, Saurabh ^{[1
]}

机构：

[1] IIT Madras, Dept Elect Engn, Chennai, Tamil Nadu, India

[2] Qualcomm, Bengaluru, India

[3] Space Applicat Ctr ISRO, Ahmadabad, Gujarat, India

来源：

2023 36TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2023 22ND INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, VLSID | 2023年

关键词：

Integer-N PLL; supply regulated wide range VCO; charge-pump with large dynamic range; PLL;

D O I：

10.1109/VLSID57277.2023.00076

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present an integer-N phase-locked loop with a 5X output frequency range. The charge -pump current and voltage-controlled oscillator's current source are digitally reconfigured for an optimum PLL bandwidth with low output jitter across the 5X frequency range. Fabricated in indigenous SCL 180nm CMOS technology, the PLL multiplies the reference frequency 15-75MHz by seven and generates a 105-525MHz output frequency. It achieves an integrated jitter of 4ps and 32.2ps at 525MHz and 105MHz, respectively. The PLL dissipates 5.6mW and 3.6mW at 525MHz and 105MHz output frequencies while operating from 1.8V supply voltage.

引用

页码：348 / 352

页数：5

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