Soft Error Immune with Enhanced Critical Charge SIC14T SRAM Cell for Avionics Applications

被引:0
作者
Ahmed, Sagheer [1 ]
Ambulkar, Jayesh [1 ]
Mondal, Debabrata [1 ]
Shah, Ambika Prasad [1 ]
机构
[1] Indian Inst Technol Jammu, Dept Elect Engn, IC ResQ Lab, Jammu 181221, Jammu & Kashmir, India
来源
2023 IFIP/IEEE 31ST INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION, VLSI-SOC | 2023年
关键词
RHBD; SRAM; SEU; SEMNU; soft-error; Static noise margin; NODE UPSET RECOVERY; LOW-POWER; DESIGN;
D O I
10.1109/VLSI-SoC57769.2023.10321888
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The impact of high-energy particles in space like cosmic rays and alpha particles flips the stored data in an SRAM cell. This paper proposes a highly reliable soft error immune with enhanced critical charge 14T (SIC14T) SRAM cell that is radiation-hardened by design and has an increased critical charge that can withstand both single-event upsets (SEU) and single-event multi-node upsets (SEMNU). We compare the performance of the proposed cell with that of other considered SRAM cells, such as the SRRD12T, RSP14T, SEA14T, and 6T SRAM cell which were simulated in 45-nm CMOS technology in Cadence Virtuoso with a supply voltage of 1V and 27 degrees C operating temperature. Both SEU and SEMNU caused at the storage node of SIC14T are successfully recovered. The proposed SRAM cell has 1.02x, 0.6x, 0.72x, and 4.64x better write stability, read access time, leakage power, and critical charge than the SRRD12T with 1.68x area overhead.
引用
收藏
页码:1 / 6
页数:6
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