Scaling aligned carbon nanotube transistors to a sub-10 nm node

Aligned semiconducting carbon nanotubes are a potential alternative to silicon in the creation of scaled field-effect transistors (FETs) due to their easy miniaturization and high energy efficiency. However, it remains unclear whether aligned nanotube transistors can be fabricated at the same dimensions as low-node silicon technology and maintaining high performance. Here we report aligned carbon nanotube FETs that can be scaled to a size corresponding to the 10 nm silicon technology node. We first fabricate nanotube FETs with a contacted gate pitch of 175 nm (achieved by scaling the gate length and contact length to 85 nm and 80 nm, respectively) that exhibit an on current of 2.24 mA & mu;m(-1) and peak transconductance of 1.64 mS & mu;m(-1); this is superior to 45 nm silicon technology node transistors in terms of size and electronic performance. Six nanotube FETs are used to create a static random-access memory cell with an area of 0.976 & mu;m(2), which is comparable with the 90 nm silicon technology node. A full-contact structure is then introduced between the metal and nanotubes to achieve a low contact resistance of 90 & omega; & mu;m and reduce the dependence on the contact length. This is used to create nanotube FETs with a contacted gate pitch of 55 nm-corresponding to the 10 nm node-with carrier mobility and Fermi velocity higher than the 10 nm silicon metal-oxide-semiconductor transistors. Aligned carbon nanotubes can be used to create six-transistor static random-access memory cells with an area of less than 1 & mu;m(2) and performance superior to cells made using 90-nm-node silicon transistors, as well as field-effect transistors with scaled contacted gate pitch comparable with the 10 nm silicon technology node.