Design and Analysis of 30 GHz CMOS Low-Noise Amplifier for 5G Communication Applications

As an initial block in the receiver front-end, LNA needs to achieve high gain with minimal noise at high frequencies. LNA designs at 5G communication have drawbacks such as increased noise figure, minimum gain, and poor linearity. A CMOS Low-Noise Amplifier for the frequency range of 30 GHz with optimization technique of current reuse technique and linearization technique is proposed and implemented to obtain maximum gain with reduced noise figure with improved linearity in this paper. The linearization technique improves the input of third-order intercept point (IIP3) of an LNA. The parameters, such as sufficient gain, low noise and enhanced linearity, are considered to design the LNA for wireless 5G communication. The proposed design shows an improvement in gain and lesser noise figure compared to conventional designs. The simulation results show that the proposed LNA provides a maximum gain of 20.6 dB, a noise figure of 3.1 dB and IIP3 of 6 dB at 30 GHz with a power consumption of 6.2 mW from a supply voltage of 1.2 V. The proposed Low-Noise Amplifier is designed and simulated in the 45 nm CMOS technology.