Single Photon Counting Readout IC With 44 e- rms ENC and 5.5 e- rms Offset Spread With Charge Sensitive Amplifier Active Feedback Discharge

The paper presents the design and measurements of a low noise integrated circuit in a CMOS 130 nm for the readout of a hybrid pixel detector operating in a single photon counting mode. A core of IC contains a matrix of 128 x 256 square shaped pixels of 75 mu m pitch. Each readout pixel consists of a charge sensitive amplifier (CSA), a shaper, two discriminators, and two 14-bit counters. We present the novel CSA feedback circuitry with an effective resistance of 0.6 GQ and sets of switches, which allows low noise operation and fast return to the CSA output baseline at the same time providing the possibility of operation with a higher flux of input pulses. The measured equivalent noise charge of IC (bump-bonded to silicon sensor) is only 44 e(-) rms at 15(?)C, the offset spread is 5.5 e(-) rms and the energy resolution is FWHM = 380 eV @ 8keV, which is currently the best result in single photon counting pixel detectors. The hybrid pixel detector can register up to 107 million photons/mm2 per second, while the power consumption per single pixel is about 42 mu W.