A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm

被引：8

作者：

Ye, Zonglin ^{[1
]}

Geng, Xinlin ^{[1
]}

Xiao, Yao ^{[1
]}

Xie, Qian ^{[1
]}

Wang, Zheng ^{[1
]}

机构：

[1] Univ Elect Sci & Technol China, Sch Integrated Circuit Sci & Engn, Chengdu 611731, Peoples R China

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2024年 / 59卷 / 03期

关键词：

Charge pump phase-locked loop (CPPLL); fractional-N; frequency synthesizer; low jitter; phase noise; spur; time-amplifying phase-frequency detector (TAPFD); SUB-SAMPLING PLL; ULTRA-LOW-JITTER; NOISE; GAIN;

D O I：

10.1109/JSSC.2023.3339679

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 24-28-GHz sub-50-fs(rms) jitter fractional-N charge pump phase-locked loop (CPPLL) is presented in this work. A dual-digital-to-time converter (DTC)-assisted time-amplifying phase-frequency detector (TAPFD) structure is proposed to suppress the in-band noise of charge pump (CP) and cancel the quantization error (QE) simultaneously while keeping low power consumption. Moreover, a cascadable DTC gear estimation and nonlinearity compensation algorithm (NLC) is also proposed to mitigate the fractional spur. The presented PLL achieves a measured integrated rms jitter including spurs of 37.1 fs with -255.2 -dB FoM(J) for integer-N channel and 45.6 fs with -253.0 -dB FoM(J) for fractional-N channel.

引用

页码：677 / 689

页数：13

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