A 10-Gb/s 275-fsec Jitter Cryo-CMOS Charge-Sampling CDR for Quantum Computing Application

被引：4

作者：

de Jong, Lennart ^{[1
]}

Bas, Joachim I. ^{[1
]}

Gong, Jiang ^{[1
]}

Sebastiano, Fabio ^{[1
]}

Babaie, Masoud ^{[1
]}

机构：

[1] Univ Technol, Dept Quantum & Comp Engn, NL-2628 Delft, Netherlands

来源：

IEEE MICROWAVE AND WIRELESS TECHNOLOGY LETTERS | 2023年 / 33卷 / 06期

关键词：

Charge-sampling phase detector (PD); clock and data recovery (CDR); cryogenic CMOS (cryo-CMOS); full-rate; low jitter; PD;

D O I：

10.1109/LMWT.2023.3267842

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This letter presents the first clock and data recovery (CDR) system operating at 4.2 K designed for quantum computing (QC) applications. By considering the benefits and challenges of cryogenic operation, a dedicated analog CDR structure is employed so as to maintain high performance at 300 and 4.2 K. The CDR incorporates a new complementary charge-sampling phase detector (PD) that achieves low power and low jitter. Fabricated in 40-nm CMOS, the proposed CDR operates at 10 Gb/s, achieving a recovered clock jitter of 260 fs and a jitter tolerance of 2 UIPP at a 5-MHz jitter frequency while consuming 4.7 mW at room temperature (RT). At 4.2 K, the power consumption reduces to 3.1 mW with a recovered clock jitter of 275 fs and a jitter tolerance of 0.85 UIPP at a 5-MHz jitter frequency, demonstrating its functionality for a high-speed cryogenic wireline link.

引用

页码：875 / 878

页数：4