Wafer-level chip-scale package lead-free solder fatigue: A critical review

Due to the increasing trend of wearable devices and micro-electromechanical systems, thinner and smaller devices are rapidly increasing in the electronic market. These devices contain advanced components such as 3D semiconductor packages which are designed for thinner and smaller electronic device applications. An example of such technology is the wafer-level chip-scale packages which have the unique characteristic of being size efficient. The whole wafer-level chip-scale package can be as small as the size of the die it contains. However, the features of the wafer-level chips-scale package also give rise to solder reliability issues due to its thinner and smaller form factor. In line with this, this review discusses the latest trend in the wafer-level chip-scale packages solder joint technology. This includes the identification of the authors, institutions, and countries focusing on the development of this technology. A bibliometric analysis is con-ducted to scientifically analyze the trend of the latest available publications and to obtain the relevant pool of publications related to the wafer-level chip-scale package solder joint reliability. The analysis resulted in three categories namely: design guidelines, innovation, and prediction category. The design guideline category reviews the current publications which focus on the effects of the different parameters on the design aspect of the wafer-level chip-scale package. The innovation category on other hand tackles the different design proposals to address different reliability issues on the solder joints of the package. At the prediction category, the different prediction models that are applicable on determining the fatigue of solder joints in the wafer-level chip-scale package. This study aims to review the status of wafer-level-scale package technology and aid researchers to innovate on the WLCSP solder joint connection through experimentation and fatigue prediction models.