Enhancement of ISPP Efficiency Using Neural Network-Based Optimization of 3-D NAND Cell

被引:2
|
作者
Cho, Kyeongrae [1 ]
Yun, Hyeok [1 ]
Nam, Kihoon [1 ]
Park, Chanyang [1 ]
Jang, Hyundong [1 ]
Yoon, Jun-Sik [1 ]
Choi, Hyun-Chul [2 ]
Park, Min Sang [3 ]
Baek, Rock-Hyun [1 ]
机构
[1] Pohang Univ Sci & Technol POSTECH, Dept Elect Engn, Pohang 37673, South Korea
[2] Yeungnam Univ, Dept Elect Engn, Gyongsan 38541, South Korea
[3] SK hynix Inc, Icheon 17336, South Korea
基金
新加坡国家研究基金会;
关键词
Artificial neural networks; Training; Semiconductor process modeling; Optimization methods; Standards; Flash memories; Structural engineering; 3-D NAND; incremental step pulse program (ISPP) slope; machine learning; NAND cell optimization; threshold voltage prediction; FLASH MEMORY;
D O I
10.1109/TED.2023.3275549
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The enhancement of program efficiency is essential for fast NAND cell operation. However, it is difficult to simultaneously consider many factors, such as structural parameters and trap characteristics, having complex relationships. To overcome these problems, we proposed a neural network (NN)-applied optimization method. First, an optimal network structure was selected by comparing the network performance and learning time. The selected network accurately predicted the threshold voltages of the 21 states of a single NAND cell within a second. Next, an optimization method to improve program efficiency is suggested. The improved NAND cell structure is obtained using a trained NN and numerical method. Here, the optimization required only a few minutes for one optimization process and could consider all parameters simultaneously. Finally, the optimized NAND cell was evaluated using a technology computer-aided design (TCAD) simulation, and its program efficiency was verified. This study shows a specific example of machine learning applied to the semiconductor area, especially in NAND flash memory.
引用
收藏
页码:3504 / 3510
页数:7
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