A Paradigm Shift in Vertical Tunneling Double Gate TFET Performance: Unveiling the Implications of Spacer-Drain Overlap

A novel double gate tunnel field-effect transistor with spacer-drain overlap (SDO-DGTFET) has been suggested and thoroughly examined. Excellent performance parameters of a proposed device such as drain induced barrier lowering (DIBL), ON-state to OFF-state current ratio (I-ON/I-OFF), drain transconductance (g(d)), sub-threshold swing (SS) and transconductance (g(m)) has been achieved. Various factors affecting the device's performance have been analyzed, including the overlap width, temperature, electric field, channel length, drain voltage, doping concentration, and metal work function variations. The proposed device gives improved DIBL of 8 mV/V, I-ON/I-OFF ratio of approximately 0.433 x 10(14)A/mu m and SS of 13 mV/decade as compared to DIBL of 17 mV/V, (I-ON/I-OFF) ratio of approximately 2.731 x 10(11) A/mu m and SS of 45 mV/decade for the single gate TFET (SG-TFET) with SDO using vertical tunneling and other existing TFET structure. The key advantage of the vertical tunneling-based SDO-DGTFET lies in its 20 nm spacer-drain overlap width, which facilitates dominant carrier tunneling aligned with the gate voltage direction. This unique feature contributes to the superior performance of the SDO-DGTFET over other TFET devices. In conclusion, the proposed vertical tunneling-based SDO-DGTFET shows promising potential for advanced electronic applications due to its outstanding performance characteristics, making it a compelling candidate for future device technologies.