5 GHz Phase-Locked Loop With a Phase-Adjusting Function

被引：6

作者：

Kuo, Yue-Fang ^{[1
]}

Kuo, Ying-Yan ^{[2
]}

Lin, Jia-Chuan ^{[2
]}

机构：

[1] Yuan Ze Univ, Dept Elect Engn, Taoyuan City 320315, Taiwan

[2] Natl Taipei Univ, Elect Engn Dept, New Taipei City 23741, Taiwan

来源：

IEEE MICROWAVE AND WIRELESS TECHNOLOGY LETTERS | 2023年 / 33卷 / 05期

关键词：

Phase locked loops; Voltage-controlled oscillators; Voltage control; Delays; Voltage; Phase frequency detectors; Semiconductor device measurement; CMOS process; frequency synthesizer; phase-locked loop (PLL); ARRAY; PLL;

D O I：

10.1109/LMWT.2023.3234657

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The design of a 5 GHz phase-locked loop (PLL) with a phase-adjusting function is presented. The voltage-controlled delay line (VCDL) is proposed to adjust the feedback signal phase by an externally controlled voltage. The output phase difference of multi-PLLs can be shifted from 0(?) to 98.6(?), when the propagation delay of VCDL is 0.41 and 4.75 ns, respectively. The proposed PLL was fabricated in TSMC 0.18-mu m CMOS process and supplied at 1.8 V with a power dissipation of 16.38 mW. The locking time is less than 2 mu s under the different controlled voltage ranges of VCDL.

引用

页码：583 / 586

页数：4

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