5 GHz Phase-Locked Loop With a Phase-Adjusting Function

被引：6

作者：

Kuo, Yue-Fang ^{[1
]}

Kuo, Ying-Yan ^{[2
]}

Lin, Jia-Chuan ^{[2
]}

机构：

[1] Yuan Ze Univ, Dept Elect Engn, Taoyuan City 320315, Taiwan

[2] Natl Taipei Univ, Elect Engn Dept, New Taipei City 23741, Taiwan

来源：

IEEE MICROWAVE AND WIRELESS TECHNOLOGY LETTERS | 2023年 / 33卷 / 05期

关键词：

Phase locked loops; Voltage-controlled oscillators; Voltage control; Delays; Voltage; Phase frequency detectors; Semiconductor device measurement; CMOS process; frequency synthesizer; phase-locked loop (PLL); ARRAY; PLL;

D O I：

10.1109/LMWT.2023.3234657

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The design of a 5 GHz phase-locked loop (PLL) with a phase-adjusting function is presented. The voltage-controlled delay line (VCDL) is proposed to adjust the feedback signal phase by an externally controlled voltage. The output phase difference of multi-PLLs can be shifted from 0(?) to 98.6(?), when the propagation delay of VCDL is 0.41 and 4.75 ns, respectively. The proposed PLL was fabricated in TSMC 0.18-mu m CMOS process and supplied at 1.8 V with a power dissipation of 16.38 mW. The locking time is less than 2 mu s under the different controlled voltage ranges of VCDL.

引用

页码：583 / 586

页数：4

共 50 条

[1] A 5-GHz injection-locked phase-locked loop
Plessas, F
Kalivas, G
MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2005, 46 (01) : 80 - 84
[2] A subharmonically injected phase-locked loop for 5-GHz applications
Plessas, Fotis
Kalivas, Grigorios
MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2006, 48 (11) : 2158 - 2162
[3] Phase-error cancellation technique for fast-lock phase-locked loop
Ding, Zhaoming
Liu, Haiqi
Li, Qiang
IET CIRCUITS DEVICES & SYSTEMS, 2016, 10 (05) : 417 - 422
[4] A 5 GHz 90-nm CMOS all digital phase-locked loop
Lu, Ping
Sjoland, Henrik
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2011, 66 (01) : 49 - 59
[5] Linear Phase-Locked Loop
Miskovic, Vlatko
Blasko, Vladimir
Jahns, Thomas M.
Lorenz, Robert D.
Jorgensen, Per M.
2018 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE), 2018, : 5677 - 5683
[6] Fault Injection Caused by Phase-Locked Loop Compromised With IEMI
Nishiyama, Hikaru
Fujimoto, Daisuke
Hayashi, Yuichi
IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2024,
[7] Single-Event Effect Characterization of 16 GHz Phase-Locked Loop in Sub-20 nm FinFET Technology
Sun, Hanhan
Wu, Zirui
Luo, Deng
Liang, Bin
Chen, Jianjun
Chi, Yaqing
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2024, 71 (09) : 2077 - 2085
[8] A Phase-Locked Loop With Inherent DC Offset Rejection for Single-Phase Applications
Smadi, Issam A.
Altabbal, Haya
Fawaz, Bayan H. Bany
IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, 2023, 19 (01) : 200 - 209
[9] A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function
Ryu, Sigang
Yeo, Hwanseok
Lee, Yoontaek
Son, Seuk
Kim, Jaeha
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2014, 49 (08) : 1773 - 1784
[10] A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique
Liang, Yuan
Boon, Chirn Chye
Qi, Gengzhen
Dziallas, Giannino
Kissinger, Dietmar
Ng, Herman Jalli
Mak, Pui-In
Wang, Yong
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2022, 70 (05) : 2642 - 2657

← 1 2 3 4 5 →