A Highly Integrated Distributed Mixer Receiver for Low-Power Wireless Radios

被引:1
作者
Bialek, Hayden [1 ]
Johnston, Matthew L. [1 ]
Natarajan, Arun [1 ]
机构
[1] Oregon State Univ, Dept Elect Engn & Comp Sci EECS, Corvallis, OR 97333 USA
基金
美国国家科学基金会;
关键词
Analog integrated circuits; circuit theory; CMOS integrated circuits; high-speed integrated circuits; integrated circuit noise; microwave integrated circuits; radio frequency integrated circuits; switched capacitor circuits; wireless sensor networks; FRONT-END; 915; MHZ; NOISE; SENSITIVITY; 2.4-GHZ; FILTERS;
D O I
10.1109/JSSC.2023.3317778
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Low-power receivers (RXs) with 100 mu W-scale power consumption can enable several power/energy-constrained Internet-of-Things (IoT) applications. However, achieving sensitivity, interferer tolerance, and wide operating range with low power presents a challenge for existing architectures, particularly those constrained to highly integrated solutions without high-QOFF-chip components. This article presents a low-power RX that utilizes a novel distributed N-path mixer architecture to enable asub-150-mu W multi-tone RX achieving wide operating range, high sensitivity and interferer tolerance. The proposed architecture is implemented in 22 nm CMOS and occupies 0.48 mm2. The RX achieves a 500-MHz operating range from 0.4 to 0.9 GHz with up to-85-dbm sensitivity for 100-kbps data rate with <150-mu Wpower consumption and up to -41-dB SIR tolerance.
引用
收藏
页码:3421 / 3432
页数:12
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