Time-triggered Network Interface Extension for the Versal Network-on-Chip

In semiconductor technology, the ability to scale up the microchip made it possible to integrate more IP blocks, microprocessors, and other components into a single die known as a System-on-Chip. Network-on-Chips are introduced to enable efficient communication between the components integrated into the System-on-Chip. However, they start to suffer from data loss and a higher jitter as the number of communicating entities increase, and communicate simultaneously. Hence establishing temporal partitions between various subsystems has become a crucial requirement. The recent advancements in Network-on-Chips have led to the development of the Versal NoC, by Xilinx. The Versal Network-on-Chip provides different Quality of Service for efficient communication; However, temporal partitioning is not sufficiently covered for messages injected into the NoC. This work develops a Time-Triggered Extension Layer for the Versal Network-on-Chip to provide temporal guarantees for messages that traverse across the NoC. The outcome applies temporal partitioning to avoid the collision of messages, thereby providing determinism for the Network-on-Chip. The results of the evaluation show reduced jitter when the developed time-triggered extension layer is incorporated into the Versal Network-on-Chip. It also safeguards the Network-on-Chip against data loss occurring when two or more PEs (Processing Elements) attempt to access the Network-on-Chip simultaneously. The implication of this work is that the Time-Triggered Extension Layer provides determinism for messages injected into the Network-on-Chip.