A 79 pW, 106 ppm/°C NMOS-only current reference with leakage current isolation based on body bias technique

被引：8

作者：

Huang, Wenjian ^{[1
,2
]}

Zeng, Yanhan ^{[1
,2
]}

Yang, Jingci ^{[1
,2
]}

Li, Yongfu ^{[3
]}

机构：

[1] Guangzhou Univ, Sch Elect & Commun Engn, Guangzhou, Peoples R China

[2] Guangzhou Univ, Dept Educ Guangdong Prov, Key Lab Si Based Informat Mat & Devices & Integrat, Guangzhou, Peoples R China

[3] Shanghai Jiao Tong Univ, Shanghai, Peoples R China

来源：

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS | 2023年 / 161卷

基金：

中国国家自然科学基金;

关键词：

Current reference; Body bias; Leakage isolation; Ultra-low-power; CURRENT REFERENCE CIRCUIT; VOLTAGE REFERENCE; COMPENSATION; GENERATOR;

D O I：

10.1016/j.aeue.2023.154539

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A pico-watt, NMOS-only current reference has been proposed and simulated using 0.18-mu m deep N-well CMOS process in this paper. To significantly reduce the power consumption to 79 pW and minimal operating voltage to 0.8 V, body bias technique is introduced. A level shift is proposed and used for isolating the N-channel/P-sub diode leakage current, which decrease the temperature coefficient to 106 ppm/degrees C when temperature changes from 0 to 125 degrees C. Besides, the line sensitivity and line regulation are obtained as 1.39%/V and 0.31%/V, respectively.

引用

页数：9

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