Design and Analysis of a Low Phase Noise Low Power Ring-VCO

被引：1

作者：

Zou, Wei ^{[1
,2
]}

Zhang, Xinyu ^{[1
,2
]}

Cheng, Zhengwang ^{[1
,2
]}

Wang, Mei ^{[1
,2
]}

Ma, Xinguo ^{[1
,2
]}

机构：

[1] Hubei Univ Technol, Natl Res Ctr Microelect & Integrated Circuits 111, 28,Nanli Rd, Wuhan 430068, Peoples R China

[2] Hubei Univ Technol, Sch Sci, 28,Nanli Rd, Wuhan 430068, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2023年 / 20卷 / 23期

关键词：

Ring-VCO; phase noise; power consumption; PLL; OSCILLATOR; CMOS; PLL; JITTER; LOOP;

D O I：

10.1587/elex.20.20230443

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low phase noise low power ring voltage-controlled oscillator (Ring-VCO) is proposed for phase-locked loops (PLLs) in the 802.11ah communication protocol band. A three-stage Ring-VCO with dual-path structure delay cells is designed to meet the high performance requirements of Internet of Things. The main noise source in the differential delay cell can be eliminated at the differential output, thus reducing phase noise. Implemented in an old TSMC 0.18 mu m CMOS process, the Ring-VCO achieves a tuning range of 343.56974.56 MHz. The phase noise at 1 MHz offset varies from-116.28 to 108.74 dBc/Hz, and the current consumed is 2.27 mA.

引用

页数：5

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