Resistor-less power-rail ESD clamp circuit design with adjustable NMOS gate biased voltage

被引：0

作者：

Li, Shuang ^{[1
,2
]}

Wang, Yang ^{[1
,2
]}

Tao, Hongke ^{[1
,2
]}

Liu, Qing ^{[1
,2
]}

Zeng, Zhiwen ^{[1
,2
]}

Jin, Xiangliang ^{[1
,3
]}

Yang, Hongjiao ^{[1
,2
]}

机构：

[1] Xiangtan Univ, Sch Phys & Optoelect, Xiangtan 411105, Hunan, Peoples R China

[2] Hunan Engn Lab Microelect Optoelect & Syst Chip, Xiangtan 411105, Hunan, Peoples R China

[3] SuperESD Microelect Technol Co Ltd, Changsha 410100, Hunan, Peoples R China

来源：

SEMICONDUCTOR SCIENCE AND TECHNOLOGY | 2023年 / 38卷 / 11期

关键词：

electrostatic discharge (ESD); big clamp NMOS (M-big); simulation; robustness; transmission line pulse (TLP) test;

D O I：

10.1088/1361-6641/ad01d3

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Based on the 0.18 mu m CMOS process, proposed a new power-rail electrostatic discharge clamp circuit. The proposed circuit can adjust the voltage biased to the big clamp NMOS (M-big) gate by adjusting the width of one MOS transistor, and the feedback path is designed to prolong the response time of Mbig. The simulation results demonstrated that the voltage biased to the M-big of the proposed circuit has a relatively steady state and the Mbig has a longer response time, which can effectively reduce the damage to the gate oxide layer of the M-big with large voltage overshoot. The transmission line pulse test results show that compared to the M-big of the conventional circuit, the M-big of the proposed circuit has higher trigger voltage, lower on-resistance, and better robustness.

引用

页数：8

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