FPGA Implementation of High-speed Communication End System (ES) Interface for Avionics Application

With the current trend of rapid development of advanced data transmission technologies in the avionics fields, the avionics buses for future Avionic applications need to cater to increased bandwidths to enable the high data transfer rates between sub-systems and the Mission Computer(MC)/On-Board Computer(OBC). Major subsystems include the Inertial Navigation System (INS), Seeker, Target Update Receiver, Warhead, Telemetry, and Global Positioning System(GPS). MC has to acquire the data from these sub-systems and carry out the required computation in real-time with periodicities of the order of 2.5ms or 5ms with deadlines of the order of 1ms. Safety critical systems like Aircraft, Missile, Launch Vehicles, and Satellites require a reliable communication protocol to guarantee their functioning without errors. Thus, Avionics Full Duplex Switched Ethernet (AFDX) shows great potential in onboard avionic systems because of its high-speed performance, redundancy, full-duplex, deterministic, switched, and profiled network. Typical data rates are of the order of 10kbps to 1Mbps. The main objective of this paper is to design of high-speed communication End System interface for avionics applications and its implementation on FPGA.