共 50 条
- [1] Automatic on-chip memory minimization for data reuse FCCM 2007: 15TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS, 2007, : 251 - +
- [2] ClosNets: Batchless DNN Training with On-Chip A Priori Sparse Neural Topologies 2018 28TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL), 2018, : 55 - 59
- [3] Accelerating DNN Training with Structured Data Gradient Pruning 2022 26TH INTERNATIONAL CONFERENCE ON PATTERN RECOGNITION (ICPR), 2022, : 2293 - 2299
- [4] DNNOPT: A Framework for Efficiently Selecting On-chip Memory Loop Optimizations of DNN Accelerators PROCEEDINGS OF THE 21ST ACM INTERNATIONAL CONFERENCE ON COMPUTING FRONTIERS 2024, CF 2024, 2024, : 126 - 137
- [5] Robustness to Variability and Asymmetry of In-Memory On-Chip Training ARTIFICIAL NEURAL NETWORKS AND MACHINE LEARNING, ICANN 2023, PT IX, 2023, 14262 : 249 - 257
- [6] Variability impact on on-chip memory data paths 2014 5TH EUROPEAN WORKSHOP ON CMOS VARIABILITY (VARI), 2014,
- [7] QOC: Quantum On-Chip Training with Parameter Shift and Gradient Pruning PROCEEDINGS OF THE 59TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC 2022, 2022, : 655 - 660
- [9] Automatic Data Placement into GPU On-Chip Memory Resources 2015 IEEE/ACM INTERNATIONAL SYMPOSIUM ON CODE GENERATION AND OPTIMIZATION (CGO), 2015, : 23 - 33