A 10-Gb/s Dual-Loop Reference-less CDR with FD Controller

被引:0
作者
Kim, Sihan [1 ]
Song, Changmin [1 ]
Kim, Jinseok [2 ]
Oh, Yonghun [2 ]
Kim, Changwan [2 ]
Jang, Young-Chan [1 ]
机构
[1] Kumoh Natl Inst Technol, Dept Elect Engn, Gumi, South Korea
[2] Uniqconn, Room 305 42 Changeop ro, Seongnam Si, Gyeonggi Do, South Korea
来源
2023 20TH INTERNATIONAL SOC DESIGN CONFERENCE, ISOCC | 2023年
关键词
Dual-loop; CDR; reference-less; Frequency Detector; Phase Detector; FD controller; DATA RECOVERY CIRCUIT; CLOCK;
D O I
10.1109/ISOCC59558.2023.10396434
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A 10-Gb/s dual-loop reference-less clock data recovery (CDR) circuit with a FD controller is proposed for serial interface applications. The proposed FD controller disables the FD loop to improve the jitter characteristics in normal operation mode after the CDR is locked in training mode. The proposed reference-less CDR is implemented using a 65nm 1 poly 9-metal CMOS process with a supply of 1.2 V. Its area containing the FD controller is 640 mu m x 480 mu m. Its power consumption is 70 mW in training mode and 55mW in operation mode. For input data encoded in 8b10b with a data rate of 10 Gb/s, a clock with a frequency of 5 GHz recovered by the proposed dual-loop reference-less CDR has a peak-to-peak time jitter of less than 2 ps.
引用
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页码:109 / 110
页数:2
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