A Two-step Linear-Exponential Incremental ADC with Slope Extended Counting

被引:1
作者
Pan, Yuhan [1 ]
Wang, Qingxun [1 ]
Chen, Kaiquan [1 ]
Cai, Bin [2 ]
Qian, Jiuchao [1 ]
Lian, Yong [3 ]
Qi, Liang [1 ]
机构
[1] Shanghai Jiao Tong Univ, Dept Micronano Elect, Shanghai, Peoples R China
[2] Shanghai Aerosp Control Technol Inst, Shanghai, Peoples R China
[3] York Univ, Toronto, ON, Canada
来源
2023 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS | 2023年
基金
中国国家自然科学基金; 国家重点研发计划;
关键词
incremental delta-sigma analog-to-digital converter (IADC); high resolution; linear-exponential; slope extended counting;
D O I
10.1109/ISCAS46773.2023.10182190
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Two-step linear-exponential architectures can be applied to incremental ADCs (IADC) to achieve high resolution. In the first step, the ADC works as a normal first-order IADC while, in the second step, the exponential integrator is used to implement extended counting. There exist two architectures for the implementation of the exponential step, where the only difference depends on whether the input signal is connected or disconnected. By conducting a comparative analysis on such two slightly different linear-exponential architectures, we propose to combine the exponential and slope techniques to further boost the resolution without degrading its original thermal-noise suppression ability and DWA effectiveness. Mathematical analysis and simulation results are presented to confirm the principle of the proposed IADC.
引用
收藏
页数:5
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