A dynamic power-efficient 4 GS/s CMOS comparator

被引：7

作者：

Dehkordi, Mehrdad Amirkhan ^{[1
]}

Dousti, Massoud ^{[1
]}

Mirsanei, Seyed Mehdi ^{[2
]}

Zohoori, Soorena ^{[3
]}

机构：

[1] Islamic Azad Univ, Dept Elect & Comp Engn, Sci & Res Branch, Tehran, Iran

[2] Islamic Azad Univ, Dept Elect Engn, Najafabad Branch, Najafabad, Iran

[3] UCL, Dept Elect & Elect Engn, London WC1E 7JE, England

来源：

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS | 2023年 / 170卷

关键词：

Latch; Pre-amplifier; Dynamic comparator; High-speed; Low-power; Power-efficiency; ADC; HIGH-SPEED; KICKBACK NOISE; DESIGN; CANCELLATION; TIME; ADC;

D O I：

10.1016/j.aeue.2023.154812

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a mid-stage latch circuit to be employed in a high-speed comparator. The advantages of the proposed circuit are low kickback noise and offset. Moreover, low-power and high-speed characteristics are obtained by avoiding direct connection between the pre-amplifier and latch stages using another stage between them. The power-delay product (PDP) of the comparator is reduced due to the reduction in charging and discharging delays at the latching nodes. The proposed comparator consumes only 244.19 & mu;W using a 1 V supply voltage. Furthermore, the bandwidth, delay, offset, and kickback noise of the proposed comparator are 4 GHz, 26.91 ps, 3 mV, and 38 mV, respectively. Results indicate the proper performance of the proposed comparator in low-power applications.

引用

页数：9

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