A Study on the Effect of Temperature Variations on FPGA-Based Multi-Channel Time-to-Digital Converters

被引:2
作者
Alshehry, Awwad H. [1 ]
Alshahry, Saleh M. [1 ]
Alhazmi, Abdullah K. [1 ]
Chodavarapu, Vamsy P. [1 ]
机构
[1] Univ Dayton, Dept Elect & Comp Engn, 300 Coll Pk, Dayton, OH 45469 USA
关键词
field programmable gate arrays; FPGA; RMS resolution; tapped delay line; temperature variations; time to digital converter; TDC; RESOLUTION; CHALLENGES; DESIGN;
D O I
10.3390/s23187672
中图分类号
O65 [分析化学];
学科分类号
070302 ; 081704 ;
摘要
We describe a study on the effect of temperature variations on multi-channel time-to-digital converters (TDCs). The objective is to study the impact of ambient thermal variations on the performance of field-programmable gate array (FPGA)-based tapped delay line (TDL) TDC systems while simultaneously meeting the requirements of high-precision time measurement, low-cost implementation, small size, and low power consumption. For our study, we chose two devices, Artix-7 and ProASIC3L, manufactured by Xilinx and Microsemi, respectively. The radiation-tolerant ProASIC3L device offers better stability in terms of thermal sensitivity and power consumption compared to the Artix-7. To assess the performance of the TDCs under varying thermal conditions, a laboratory thermal chamber was utilized to maintain ambient temperatures ranging from -75 to 80 & DEG;C. This analysis ensured a comprehensive evaluation of the TDCs' performance across a wide operational range. By utilizing the Artix-7 and ProASIC3L devices, we achieved root mean square (RMS) resolution of 24.7 and 554.59 picoseconds, respectively. Total on-chip power of 0.968 W was achieved using Artix-7, while 1.997 mW of power consumption was achieved using the ProASIC3L device. We worked to determine the temperature sensitivity for both FPGA devices, which could help in the design and optimization of FPGA-based TDCs for many applications.
引用
收藏
页数:17
相关论文
共 45 条
[1]   A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method [J].
Alshahry, Saleh M. ;
Alshehry, Awwad H. ;
Alhazmi, Abdullah K. ;
Chodavarapu, Vamsy P. .
SENSORS, 2023, 23 (14)
[2]  
[Anonymous], 2012, Xilinx 7 Series FPGA Libraries, V7991653
[3]  
Bayer E., 2010, P 2010 17 IEEE NPSS, P1
[4]   Evaluation of optical ranging and frequency transfer for the Kepler system : preliminary laboratory tests [J].
Calvo, Ramon Mata ;
Poliak, Juraj ;
Surof, Janis ;
Wolf, Raphael .
2020 EUROPEAN NAVIGATION CONFERENCE (ENC), 2020,
[5]   Recent Developments and Design Challenges of High-Performance Ring Oscillator CMOS Time-to-Digital Converters [J].
Cheng, Zeng ;
Zheng, Xiaoqing ;
Deen, M. Jamal ;
Peng, Hao .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (01) :235-251
[6]   A Tunable Parameter, High Linearity Time-to-Digital Converter Implemented in 28-nm FPGA [J].
Deng, Jun ;
Yin, Peng ;
Lei, Xin ;
Shu, Zhou ;
Tang, Mingchun ;
Tang, Fang .
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2021, 70
[7]  
Digilent Inc., Arty-A7 Reference Manual
[8]   A High-Density Time-to-Digital Converter Prototype Module for BES III End-Cap TOF Upgrade [J].
Fan, Huanhuan ;
Feng, Changqing ;
Sun, Weijia ;
Yin, Chunyan ;
Liu, Shubin ;
An, Qi .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2013, 60 (05) :3563-3569
[9]  
Favi Claudio., 2009, Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, P113, DOI DOI 10.1145/1508128.1508145
[10]   Time-to-Digital Converter IP-Core for FPGA at State of the Art [J].
Garzetti, Fabio ;
Corna, Nicola ;
Lusardi, Nicola ;
Geraci, Angelo .
IEEE ACCESS, 2021, 9 :85515-85528